IndiumV3, Main, Repository, bibRecord, 000C95

Ferroelectric transistor memory arrays on flexible foils

Identifieur interne : 000C95 ( Main/Repository ); précédent : 000C94; suivant : 000C96

Ferroelectric transistor memory arrays on flexible foils

Auteurs : RBID : Pascal:13-0218248

Descripteurs français

Pascal (Inist)
- Mémoire ferroélectrique, Transistor mémoire, Dispositif à mémoire, Annihilation positon, Composant électronique, Densité intégration, Modulation, Facteur rétention, Commutation, Régime fonctionnement, Vitesse déplacement, Commutateur, Effet champ électrique, Champ électrique, Mémoire non volatile, Vinylidène fluorure copolymère, Ethylène(trifluoro) copolymère, Réseau (arrangement), Oxyde d'indium, Oxyde de gallium, Oxyde de zinc, Semiconducteur, Ferroélectrique, Circuit intégré, 7784, Polymère ferroélectrique.
Wicri :
- concept : Composant électronique.

English descriptors

KwdEn :
- Array, Electric field, Electric field effect, Electronic component, Ferroelectric materials, Ferroelectric polymer, Ferroelectric storage, Gallium oxide, Indium oxide, Integrated circuit, Integration density, Memory devices, Memory transistor, Modulation, Non volatile memory, Operating rate, Positron annihilation, Retention factor, Selector switch, Semiconductor materials, Speed, Switching, Trifluoroethylene copolymer, Vinylidene fluoride copolymer, Zinc oxide.

Abstract

In this paper, we successfully fabricated and operated passive matrix P(VDF-TrFE) transistor arrays, i.e. memory arrays in which no pass-transistors or other additional electronic components are used. Because of the smaller cell, a higher integration density is possible. We demonstrate arrays up to a size of 16 × 16, processed on thin (25 μm) poly(ethylene naphthalate) substrates, using Indium-Gallium-Zinc-Oxide (IGZO) as the semiconductor and 200 nm-thick P(VDF-TrFE) as a ferroelectric gate dielectric. The memory transistors have remnant current modulations of ∼10⁵ with a retention time of more than 12 days. They can be switched in less than 1 μs at operating voltages of 25 V. Switching speed is strongly decreased with decreasing voltage: at ∼10 V the transistors do not switch within 10 s. This difference in switching speed of more than 4 orders in magnitude when changing the electric field by a factor of only 2.5 makes these memories robust towards disturb voltages, and forms the basis of integration of these transistors in passive matrix-addressable transistor arrays that contains only one (memory) transistor per cell. It is shown that with current technology and memory characteristics it is possible to scale up the array size in the future. .

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Pascal:13-0218248

Le document en format XML

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<term>Non volatile memory</term>
<term>Operating rate</term>
<term>Positron annihilation</term>
<term>Retention factor</term>
<term>Selector switch</term>
<term>Semiconductor materials</term>
<term>Speed</term>
<term>Switching</term>
<term>Trifluoroethylene copolymer</term>
<term>Vinylidene fluoride copolymer</term>
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<term>Transistor mémoire</term>
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<front><div type="abstract" xml:lang="en">In this paper, we successfully fabricated and operated passive matrix P(VDF-TrFE) transistor arrays, i.e. memory arrays in which no pass-transistors or other additional electronic components are used. Because of the smaller cell, a higher integration density is possible. We demonstrate arrays up to a size of 16 × 16, processed on thin (25 μm) poly(ethylene naphthalate) substrates, using Indium-Gallium-Zinc-Oxide (IGZO) as the semiconductor and 200 nm-thick P(VDF-TrFE) as a ferroelectric gate dielectric. The memory transistors have remnant current modulations of ∼10<sup>5</sup>
 with a retention time of more than 12 days. They can be switched in less than 1 μs at operating voltages of 25 V. Switching speed is strongly decreased with decreasing voltage: at ∼10 V the transistors do not switch within 10 s. This difference in switching speed of more than 4 orders in magnitude when changing the electric field by a factor of only 2.5 makes these memories robust towards disturb voltages, and forms the basis of integration of these transistors in passive matrix-addressable transistor arrays that contains only one (memory) transistor per cell. It is shown that with current technology and memory characteristics it is possible to scale up the array size in the future. .</div>
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<fC01 i1="01" l="ENG"><s0>In this paper, we successfully fabricated and operated passive matrix P(VDF-TrFE) transistor arrays, i.e. memory arrays in which no pass-transistors or other additional electronic components are used. Because of the smaller cell, a higher integration density is possible. We demonstrate arrays up to a size of 16 × 16, processed on thin (25 μm) poly(ethylene naphthalate) substrates, using Indium-Gallium-Zinc-Oxide (IGZO) as the semiconductor and 200 nm-thick P(VDF-TrFE) as a ferroelectric gate dielectric. The memory transistors have remnant current modulations of ∼10<sup>5</sup>
 with a retention time of more than 12 days. They can be switched in less than 1 μs at operating voltages of 25 V. Switching speed is strongly decreased with decreasing voltage: at ∼10 V the transistors do not switch within 10 s. This difference in switching speed of more than 4 orders in magnitude when changing the electric field by a factor of only 2.5 makes these memories robust towards disturb voltages, and forms the basis of integration of these transistors in passive matrix-addressable transistor arrays that contains only one (memory) transistor per cell. It is shown that with current technology and memory characteristics it is possible to scale up the array size in the future. .</s0>
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<fC03 i1="19" i2="X" l="FRE"><s0>Oxyde d'indium</s0>
<s5>25</s5>
</fC03>
<fC03 i1="19" i2="X" l="ENG"><s0>Indium oxide</s0>
<s5>25</s5>
</fC03>
<fC03 i1="19" i2="X" l="SPA"><s0>Indio óxido</s0>
<s5>25</s5>
</fC03>
<fC03 i1="20" i2="X" l="FRE"><s0>Oxyde de gallium</s0>
<s5>26</s5>
</fC03>
<fC03 i1="20" i2="X" l="ENG"><s0>Gallium oxide</s0>
<s5>26</s5>
</fC03>
<fC03 i1="20" i2="X" l="SPA"><s0>Galio óxido</s0>
<s5>26</s5>
</fC03>
<fC03 i1="21" i2="X" l="FRE"><s0>Oxyde de zinc</s0>
<s5>27</s5>
</fC03>
<fC03 i1="21" i2="X" l="ENG"><s0>Zinc oxide</s0>
<s5>27</s5>
</fC03>
<fC03 i1="21" i2="X" l="SPA"><s0>Zinc óxido</s0>
<s5>27</s5>
</fC03>
<fC03 i1="22" i2="X" l="FRE"><s0>Semiconducteur</s0>
<s5>28</s5>
</fC03>
<fC03 i1="22" i2="X" l="ENG"><s0>Semiconductor materials</s0>
<s5>28</s5>
</fC03>
<fC03 i1="22" i2="X" l="SPA"><s0>Semiconductor(material)</s0>
<s5>28</s5>
</fC03>
<fC03 i1="23" i2="X" l="FRE"><s0>Ferroélectrique</s0>
<s5>29</s5>
</fC03>
<fC03 i1="23" i2="X" l="ENG"><s0>Ferroelectric materials</s0>
<s5>29</s5>
</fC03>
<fC03 i1="23" i2="X" l="SPA"><s0>Material ferroeléctrico</s0>
<s5>29</s5>
</fC03>
<fC03 i1="24" i2="X" l="FRE"><s0>Circuit intégré</s0>
<s5>46</s5>
</fC03>
<fC03 i1="24" i2="X" l="ENG"><s0>Integrated circuit</s0>
<s5>46</s5>
</fC03>
<fC03 i1="24" i2="X" l="SPA"><s0>Circuito integrado</s0>
<s5>46</s5>
</fC03>
<fC03 i1="25" i2="X" l="FRE"><s0>7784</s0>
<s4>INC</s4>
<s5>56</s5>
</fC03>
<fC03 i1="26" i2="X" l="FRE"><s0>Polymère ferroélectrique</s0>
<s4>CD</s4>
<s5>96</s5>
</fC03>
<fC03 i1="26" i2="X" l="ENG"><s0>Ferroelectric polymer</s0>
<s4>CD</s4>
<s5>96</s5>
</fC03>
<fN21><s1>203</s1>
</fN21>
<fN44 i1="01"><s1>OTO</s1>
</fN44>
<fN82><s1>OTO</s1>
</fN82>
</pA>
</standard>
</inist>
</record>

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   |texte=   Ferroelectric transistor memory arrays on flexible foils
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Data generation: Mon Jun 9 10:27:54 2014. Site generation: Thu Mar 7 16:19:59 2024

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Ferroelectric transistor memory arrays on flexible foils

Ferroelectric transistor memory arrays on flexible foils

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English descriptors

Abstract

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